============================================================== Guild: wafer.space Community Channel: Information / general / 3.3V SRAM After: 11/30/2025 23:59 Before: 01/01/2026 00:00 ============================================================== [12/02/2025 18:47] rtimothyedwards_19428 I have finished both SRAMs (256 byte and 512 byte), all completely DRC clean with respect to both magic and klayout, and LVS verified with magic and netgen. {Reactions} blobclap 🎉 [12/02/2025 22:07] 246tnt Do you have them in a test chip though ? 😅 [12/03/2025 01:10] rtimothyedwards_19428 Working on it. I have the picoRV32 openframe project from sky130, and porting it isn't too hard. Getting it synthesized and verified in one day. . . That might be tough (although the sky130 version was synthesized and manufactured, so the configuration files exist). Worst case---I'll just drop a couple of SRAM modules directly into a user project and wire up the I/O by hand. [12/03/2025 02:19] mithro_ @Tim Edwards - I think we have a bunch of empty 0.5x1 and 1x0.5 slots - it would be great to just have a bunch of SRAM connected to I/O there... [12/03/2025 02:19] rtimothyedwards_19428 Does anybody happen to know if the `CEN` input to the SRAMs (this applies to the 5V SRAMs as well) is supposed to be always high after reset? Based on some other implementation of Caravel (which was probably for SkyWater), I have `CEN` toggling with the `valid` signal on the wishbone bus. I'm not sure if the SRAM is supposed to be operated that way. [12/03/2025 02:20] rtimothyedwards_19428 @Tim 'mithro' Ansell : I'd have to prepare a 0.5 x 1 mm padframe, though. How much time are you willing to give me to do that? [12/03/2025 02:20] mithro_ There was some discussion around it being confusingly name -- I think it was It's CE_N, not C_EN [12/03/2025 02:20] mithro_ @Tim Edwards - I ***believe*** @Leo Moser (mole99) has/had some prepare padframe for those layouts? [12/03/2025 02:22] mithro_ Or do you have custom I/Os too? [12/03/2025 02:22] rtimothyedwards_19428 @Tim 'mithro' Ansell : I admit that I have not looked at the tapeout deadline specifics. What is the last time to get something in? [12/03/2025 02:23] rtimothyedwards_19428 @Tim 'mithro' Ansell : Yes, I have custom I/Os, although in principle the 5V I/Os also work at 3.3V and could be used to test the SRAM. [12/03/2025 02:23] mithro_ Current @ {Attachments} 2025-12_media/image-DA18F.png [12/03/2025 02:24] mithro_ I'm still waiting for some information from GF which might affect that [12/03/2025 02:24] mithro_ https://www.timeanddate.com/worldclock/fixedtime.html?iso=20251203T2359&p1=3399 {Embed} https://www.timeanddate.com/worldclock/fixedtime.html?iso=20251203T2359&p1=3399 Event Time Announcer Event Time Announcer shows time for an event in locations all over the world. In Baker Island it happens on Wednesday, December 3, 2025 at 11:59:00 pm. 2025-12_media/worldclock_og-17069.php [12/03/2025 02:26] mithro_ [12/03/2025 07:26] mole99 The area and padring definitions for the slots are in: https://github.com/wafer-space/gf180mcu-project-template/tree/main/librelane/slots The CI builds a chip with all four different slot sizes, so you can grab a GDS from the Artifacts section at the very bottom: https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19820104811 [12/03/2025 07:29] mole99 @Tim Edwards, have you run the precheck on your design yet? You can do so via the online platform: https://platform.wafer.space Or, if that doesn't work, you can pass it to me and I can run the precheck locally for you. [12/11/2025 21:30] rtimothyedwards_19428 Surprisingly, I found out today that there is an "A[9]" line in the GF SRAM block, and it's connected to row decode circuitry, so at least logically, it's possible to extend the 512 byte SRAM to 1024 bytes. So I did, and added the block to my test chip. It's possible that there's a _reason_ that GF didn't have a 1024k macro for their 5V SRAM, and just tied off the A[9] line internally. But worth finding out! {Reactions} 👍 👏 [12/11/2025 21:33] rtimothyedwards_19428 Also, since my SRAM test chip was failing antenna checks, I took the opportunity to add antenna tie-downs on all the input pins of the 3.3V SRAM macros that were connected only to FET gates internally. I'm running the antenna check on the result now; hopefully that prevents many future issues with the SRAM blocks. Should try to do the same to the 5V SRAMs. There's plenty of room right at the bottom to place a contact and a small piece of diffusion under each input line except for the address lines, and the address lines are going through some transmission gate so they're already connected to diffusion and don't need the antenna diode. [12/11/2025 22:26] 246tnt I'm wondering, did you draw a schematic / architecure for the SRAM ? [12/11/2025 23:00] rtimothyedwards_19428 No, that's on my to-do list. I don't think I will be able to create a valid netlist for the 1kB SRAM without a schematic, though. The existing netlists were generated with Calibre and are not schematic captured (and are, frankly, a big mess), so it needs doing and will get done when I get around to it. For now I'm depending on the simplicity of converting the 512 byte layout to 1kB to be able to eyeball the LVS, but I hope to get proper LVS done before the Wafer.Space tapeout deadline passes. [12/17/2025 00:00] rtimothyedwards_19428 @tnt : Today's update to the repository: Complete schematics for all three SRAM blocks. {Reactions} 🎉 (3) ============================================================== Exported 22 message(s) ==============================================================